1. Field of the Invention
This invention relates to a method and computer program for extraction of wire capacitances in LSI devices having diagonal wires, and in particular relates to a method and computer program for wire capacitance extraction enabling simplification of the wire capacitance extraction process when diagonal wires are included in the LSI device.
2. Description of the Related Art
LSI device design processes are normally performed with a CAD tool executed by a computer. LSI device design processes generally include a logic design process to design the logic circuitry connecting logic gates; a layout design process to lay out the logic circuitry on an actual chip; a process to extract RLC values (resistances, inductances, capacitances) of the layout interconnects from the layout data, and to determine delay times for each signal path from the extracted RLC values and from cell and macro AC characteristics; a timing verification (logic verification) process to check, using these delay times, whether the logic circuit operates normally; and a physical verification process to check whether the layout data satisfies design rules. Through layout design, the layout data including wiring pattern data for each layer on the chip is created, and based on this layout data the RLC values for interconnects are extracted. The RLC extraction process, delay time calculation process, and logic simulation process are each realized by execution of a program by a computer.
In the above RLC extraction process, RLC values in an adjacent wire structure of actual interconnects can be calculated based on the layout data (see for example Japanese Patent Laid-open No. 2002-299456), but use of such a method requires a large amount of computer processing in the extraction process. Hence a method has been proposed of referencing an RLC rule table generated in advance according to wire widths, distances from adjacent wires, overlap areas, and other parameters, to extract from the rule table the RLC values corresponding to parameters matching the wire widths, adjacent wire distances, and overlap areas contained in the layout data (see for example Japanese Patent Laid-open No. 2002-368088, FIGS. 1 and 12). By extracting values through such matching, processing to compute RLC values can be eliminated.
Whichever method is used, the wire of interest is divided into segments according to the surrounding wire structure, and the above RLC extraction is performed for each segment. For example, the capacitance value of a wire of interest is determined by the distance of the wire of interest from adjacent wires and the overlap area, so that when extracting the capacitance value, distances from adjacent wires and areas must be extracted from layout data and used as parameters to extract the capacitance value. For the resistance value, the cross-sectional area and length of the wire of interest are necessary, and for the inductance, the length and other properties of the wire of interest are needed.